1. Field of the Invention
The present invention relates to a semiconductor integrated circuit incorporating a large-capacity memory and, more particularly, to a semiconductor integrated circuit capable of realizing downsizing of a package and reduction in number of inspection patterns.
2. Description of the Prior Art
Semiconductor integrated circuits incorporating memories have conventionally been provided. When the incorporated memory of such a semiconductor integrated circuit is to be tested, to supply an address signal indicating the address in the memory or a data signal as data to be written at this address of the memory, these signals must be supplied from the outside by an LSI tester or the like.
For this reason, a conventional semiconductor integrated circuit needs externally connectable pins in a number proportional to the memory capacity, and the number of pins increases in accordance with an increase in memory capacity. When the number of pins increases in this manner, downsizing of the package is interfered with. When the number of pins of the semiconductor integrated circuit increases, the number of probes of the LSI tester also increases, leading to an increase in cost of the test process.
In order to cope with these problems, for example, an integrated circuit disclosed in Japanese Unexamined Patent Publication No. 5-289953 has, regarding an address signal, a counting means and a decoding means. The counting means counts continuously input clock signals. The decoding means decodes a count output from the counting means to generate a select signal that specifies one memory among a plurality of memories, and to generate the address of the specified memory. The package of the integrated circuit accordingly requires neither a test address input pin nor a memory select pin.
FIG. 1 is a block diagram of the integrated circuit disclosed in this Japanese Unexamined Patent Publication No. 5-289953.
This integrated circuit has, as pins to be connected to the outside, a data input pin 1, clock (CLK) pin 2, test reset pin 3, test mode pin 4, and data output pin 5. Each of memories 6, 7, 8, and 9 is a RAM or ROM. Data from the memory 6, 7, 8, or 9 is selected by an output selector 13 that has received an output select signal S1 from a control circuit 10, and is output from the data output pin 5.
The control circuit 10 has a memory address generating counter 11 and memory selector 12. The memory address generating counter 11 counts clock pulses input from the clock pin 2. The count of the memory address generating counter 11 forms an address signal S2 indicating the memory address of either one of the memories 6, 7, 8, and 9. The memory selector 12 outputs an output select signal that selects either one of the memories 6, 7, 8, and 9 upon reception of a predetermined bit of the count of the memory address generating counter 11.
Referring to FIG. 1, in this conventional integrated circuit, as data to be written in the memory 6, 7, 8, or 9, test data is supplied from the data input pin 1. In order to inspect whether the data written in the memory 6, 7, 8, or 9 is correct, the written data is read out from the memory 6, 7, 8, or 9 to output data, and the output data is compared with the input data.
For this reason, in this conventional integrated circuit, a data input pin equivalent to the bit width of the incorporated memory is required. As the bit width of the memory increases, the number of pins increases to accordingly interfere with downsizing of the package.
Furthermore, in order to input/output the test data, the number of inspection patterns increases in proportion to the memory capacity. Accordingly, the test time required for inspection prolongs to increase the cost of inspection.